1. Field of the Invention
The invention relates to a structure of combined passive elements and logic circuits, and more particularly to a structure of combined passive elements and logic circuits on a SOI (Silicon On Insulator) wafer, which combined passive elements include resistors, inductors, capacitors and logic devices formed on a SOI wafer by using dual damascene technology, so that the layout area can be significantly decreased.
2. Description of the Related Art
In the semiconductor manufacture process, the damascene technology is an interconnects process, in which a groove is formed in an insulating layer and the groove is filled with metal to form a pin. Dual damascene is a multilevel interconnects process, in which not only a single groove, but also a via opening is formed.
For example, in the standard dual damascene process, an insulating layer is coated with a photoresist material. In this process, the photoresist layer is exposed to form a first mask with a via opening pattern, and the top of insulating layer is anisotropically etched to form the pattern. After removing the photoresist layer that has been transferred, the insulating layer is then coated with a photoresist material. In this process, the photoresist layer is exposed to form a second mask with the via opening alignment pattern. While etching the pin layer opening in the top of insulating layer, the via opening in the top of insulating layer is etched to the bottom of the insulating layer. When the etching process is finished, the via opening and the groove are then filled with metal. Dual damascene can be improved in a single metal damascene, because the dual damascene process allows the via opening and the groove to be filled with metal, simultaneously, so that many process steps can be eliminated. Therefore, the dual damascene process is a key technology to push the design rule for sub-0.18 um or lower technology.
The SOI technology is a new technology that has been employed throughout the wafer manufacturing industry. Compared to the device formed on a bulk wafer, the device formed on a SOI wafer has more advantages. For example, the SOI device has a lower power consumption, a low threshold operation and high performance advantages. These qualities are the result of manufacturing the silicon device in an isolated substrate so as to avoid the conventionally problematic inherent parasitic capacitance in the junction capacitor. Therefore, the reason for improving the SOI technology is to reduce parasitic capacitance so that the power consumption is minimized and operation speed in a specific dimension device is maximized. The use of a SOI wafer can disable the latch up effect in CMOS, and can decrease the soft error effect in MOS as well as increase the circuit operation speed.
In the conventional passive element fabrication process, which requires many complex steps, especially in the process in logic circuit of passive element, multilevel metal interconnects are a major key technology. As the process technology progresses to a level such as 0.18 um or less, device dimension is tends to be fabricated with the minimum size.
For a mixed mode circuit, many passive elements such as inductors, capacitors and resistors are required. Furthermore, due to products with increasingly smaller size, such as the notebook computer, fabrication of many devices with smaller dimensions is required. Hence, how to combine many different devices on a chip in order to reduce layout area is a present aspect of development.